(a) Field of the Invention
The present invention relates to a flash memory cell and a method for manufacturing the same, and in particular, to the flash memory cell and a method for manufacturing the same that are capable of minimizing resistance of the common source line in a fabrication process for an Embedded Flash Memory Cell.
(b) Description of the Related Art
Typically, a flash memory device is manufactured so as to secure the advantages of the EPROM having programmable and erasable characteristics, and the EEPROM having electrically programmable and erasable characteristics. Such a flash memory includes a thin tunnel oxide formed on a silicon substrate, a floating gate and a control gate deposited with an interposed dielectric film, and a source/drain region formed on an exposed area of the substrate, the device storing 1 bit at one transistor and being electrically programmable and erasable.
Such a flash memory device is provided with a source connection layer coupling a source of a unit cell for forming a source line. This source connection layer can be formed by means of a metal contact to the source of the unit cell from an overlying metal line. However, metal contacts from adjoining flash memory cells to an overlying metal common source line may not be appropriate for a large scale integrated circuit in consideration of the contact margin and cell real estate consumed by the metal source line.
Accordingly, in order to implement large scale integration of the device, a source line, which is formed from an impurity diffusion layer through a self aligned source (SAS) process, has recently been adopted. That is, the SAS process may be carried out by exposing a source region of the cell using a SAS mask while or after forming a gate electrode having a layered structure, and removing a field oxide in the exposed source region by anisotropic etching to form the common source line with an adjacent cell.
Such techniques related to the SAS process are disclosed in U.S. Pat. Nos. 5,837,584 and 6,242,305.
FIGS. 1 and 2 are drawings for illustrating the self aligned source (SAS) technique. FIG. 1 is a drawing for illustrating a cell size when the SAS technique is not adopted, and FIG. 2 is a drawing for the cell size when the SAS technique is adopted. In the above-mentioned SAS technique, the cell size shrinks in a bit line (BL) direction; i.e., the gate to source space denoted by reference d in FIG. 1 is eliminated in FIG. 2. It is believed that the SAS technique is an essential process for a commercially competitive 0.25 μm technology. By introducing the SAS technique, the cell size can be reduced by as much as 20%.
In FIG. 1, reference numeral 11 denotes a common source line (e.g., an overlying metal line) over the source region in memory cells which do not adopt the SAS technique, reference numeral 13 denotes a gate line extended in a direction of (e.g., parallel to) a word line (WL), reference numeral 15 denotes a drain, reference numeral 17 denotes a drain contact, and reference numeral 19 denotes a trench line functioning as a device isolation region, formed using shallow trench isolation (STI).
However, the conventional SAS technique depicted in FIG. 2 has a drawback in that the contact resistance of the common source line 12 per cell abruptly increases since the common source line in the memory cell adopting such a SAS technique is formed according to a profile of the trench line. Particularly, in most memory cells manufactured by 0.25 μm, 0.18 μm, or thinner μm technologies, shallow trench isolation (STI) is used as the isolation technique. STI and SAS are essential techniques for reducing the cell size in respective WL and BL directions, but the use of both techniques dramatically increases the source resistance.
Flash memory typically uses a high internal voltage. Thus, with successively smaller generations of process technology, the depth of the trench typically does not decrease in proportion to any decreases in the cell size. Accordingly, the proportional length of the common source line increases such that the cumulative source resistance may have an adverse effect over relatively long distances (e.g., 8, 16, 32 or more cells in a given wordline). Also, in the case of embedded flash, the product can be negatively affected, for example, programming characteristics and reading speed may decrease as a result of such cumulative source resistances.